1. Field of the Invention
The present invention relates to techniques for determining routing of data paths in interconnect circuitry of an integrated circuit.
2. Description of the Prior Art
Current design tools, such as digital layout EDA (electronic design automation) tools used in an ASIC (application specific integrated circuit) design flow process, have a severe limitation in achieving high accuracy in delay matching for timing critical data paths of interconnect circuitry, such as may be required for high speed nets and busses in deep submicron processes. This limitation is primarily due to how EDA tools approach the problem.
The current digital layout EDA tools use timing constraints as the requirement for the design layout. This is often referred to “timing driven place and route”. This presents the ASIC layout tool with a practically unlimited number of layout implementations. Faced with this dilemma, EDA tool often use heuristic algorithms to automatically generate ASIC layouts, heuristic algorithms being algorithms which are not designed to determine the optimal solution, but instead are aimed at finding a feasible solution that, in objective function terms, is close to the optimal solution. The initial placement and route of the design rarely satisfies the design timing constraints. As a result the layout tools resort to iterations in place and route of the timing critical portions of the design with the hope of meeting the design timing constraints.
When the design requirements are very restrictive, as for example is typically the case for high speed balanced bus interconnects, the layout iterations often do not converge, and the tool hence fails to generate a usable layout. When the layout tool does succeed in meeting the design requirements, the layouts generated are without symmetry in either element placement or signal routing. Nets are of random length and randomly jump from layer to layer. The resulting capacitance, resistance, coupling and inductance of each net cannot be accurately managed. This results in timing uncertainty in the layout.
Known digital layout EDA tools use several techniques for improving timing. Those techniques include: replacing one driving element with another with the same function but different drive strength; inserting buffers on critical paths to speed or slowdown delay; and/or breaking a long net with repeater buffers; moving critical cells physically closer. The timing variation from those approaches is quantized and introduces timing uncertainties. The matching between different timing critical paths is also greatly reduced over process corners, as those paths are built with different numbers of elements or with elements having different driving characteristics. The different elements' timing characteristics do not scale the same over process-temperature-voltage corners. Meeting one corner often mismatches other corners.
Due to the heuristic nature of the digital EDA layout algorithms, the same design can generate drastically different layouts with different tool versions or versions from different vendors. Often the same tool will produce a different layout with the same design when the layout procedure is repeated.
Another limitation of the current digital EDA layout flow is the inability of the tools to work with differential signalling, this being a method of transmitting information electrically by means of two complementary signals sent on two separate wires. Such differential signalling techniques can enable accurate propagation of fast signals though a noisy environment, such as for example are produced by the switching of digital gates.
As result, the known digital layout EDA tools and ASIC flows cannot produce design layouts that requiring a high degree of delay matching and noise immunity of the critical timing paths, nets and busses (referred to herein as “data paths”) within interconnect circuitry.
The limitations of known digital layout EDA tools are exaggerated when different bits of a bus must be routed to design blocks which are not physically close together, yet require matched timing. DDR (double data rate) memory interfaces are a good example of this limitation. DDR memory achieves nearly twice the bandwidth of non-DDR (single data rate) memory by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency. The DDR Memory Controller has a relatively small layout with respect to the span of input/output (I/O) devices to which it must connect, and this places significant timing issues on the design of the interconnect circuitry to be used to couple the memory controller with those distributed I/O devices.
As an example, DDR3 is a parallel interface that uses both edges of the clock for reading and writing data from an off-chip SDRAM at data rates as high as 1600 Mbs. The timing relationship between the data signals DQ, the strobe signal DQS, and the clock signal CK must be tightly controlled, yet the I/O devices for this design may span more than 2 mm linearly (i.e. many orders of magnitude larger than the size of the memory controller block).
Budgeting for uncontrollable timing uncertainties such as clock jitter, on-chip-variation, process-voltage-temperature variations, printed circuit board trace variations, system noise and SDRAM setup and hold timing, requires propagation delay of the data paths within the interconnect circuitry between the Memory Controller and the I/O devices to be matched within tens of nanoseconds. Given interconnect delay which is in the region of hundreds of nanoseconds for nets of 2 mm or more, the design of such interconnect circuitry is difficult to achieve with the current digital layout EDA tools.
Accordingly it would be desirable to provide an improved technique for determining routing of data paths in interconnect circuitry of an integrated circuit, which allows high accuracy in delay matching between the various data paths.